Analysis and implementation of practical, cost-effective networks on chips
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Lee, SJ | ko |
| dc.contributor.author | Lee, K | ko |
| dc.contributor.author | Yoo, Hoi-Jun | ko |
| dc.date.accessioned | 2008-07-22T06:04:44Z | - |
| dc.date.available | 2008-07-22T06:04:44Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2005-09 | - |
| dc.identifier.citation | IEEE DESIGN & TEST OF COMPUTERS, v.22, pp.422 - 433 | - |
| dc.identifier.issn | 0740-7475 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/6261 | - |
| dc.description | This article describes design issues in three chips that exploit star and mesh networks, with the objective of comparing area and energy costs. The authors present new solutions based on mesochronous communication and burst packet transactions. | en |
| dc.description.abstract | This article describes design issues in three chips that exploit star and mesh networks, with the objective of comparing area and energy costs. The authors present new solutions based on mesochronous communication and burst packet transactions. | - |
| dc.language | English | - |
| dc.language.iso | en_US | en |
| dc.publisher | IEEE COMPUTER SOC | - |
| dc.title | Analysis and implementation of practical, cost-effective networks on chips | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000231826100007 | - |
| dc.identifier.scopusid | 2-s2.0-27344452711 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 22 | - |
| dc.citation.beginningpage | 422 | - |
| dc.citation.endingpage | 433 | - |
| dc.citation.publicationname | IEEE DESIGN & TEST OF COMPUTERS | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
| dc.contributor.nonIdAuthor | Lee, SJ | - |
| dc.contributor.nonIdAuthor | Lee, K | - |
| dc.type.journalArticle | Article | - |
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