Analysis and implementation of practical, cost-effective networks on chips

This article describes design issues in three chips that exploit star and mesh networks, with the objective of comparing area and energy costs. The authors present new solutions based on mesochronous communication and burst packet transactions.
Publisher
IEEE COMPUTER SOC
Issue Date
2005-09
Language
ENG
Description

This article describes design issues in three chips that exploit star and mesh networks, with the objective of comparing area and energy costs. The authors present new solutions based on mesochronous communication and burst packet transactions.

Citation

IEEE DESIGN & TEST OF COMPUTERS, v.22, pp.422 - 433

ISSN
0740-7475
URI
http://hdl.handle.net/10203/6261
Appears in Collection
EE-Journal Papers(저널논문)
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