A 155-mW 50-mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications

Cited 28 time in webofscience Cited 33 time in scopus
  • Hit : 1685
  • Download : 1756
DC FieldValueLanguage
dc.contributor.authorSohn, JHko
dc.contributor.authorWoo, JHko
dc.contributor.authorLee, MWko
dc.contributor.authorKim, HJko
dc.contributor.authorWoo, Rko
dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2008-07-22T05:07:21Z-
dc.date.available2008-07-22T05:07:21Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2006-05-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.41, pp.1081 - 1091-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/6251-
dc.description.abstractA 36 mm(2) graphics processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) graphics applications. The graphics processor contains an ARM-10 compatible 32-bit RISC processor, a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD) vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional graphics hardware, the proposed graphics processor implements ARM-10 co-processor architecture with dual operations so that user-programmable vertex shading is possible for advanced graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the graphics processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak graphics performance, dissipating 155 mW in 0.18-mu m 6-metal standard CMOS logic process.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDECODER-
dc.subjectLSI-
dc.titleA 155-mW 50-mvertices/s graphics processor with fixed-point programmable vertex shader for mobile applications-
dc.typeArticle-
dc.identifier.wosid000237210500009-
dc.identifier.scopusid2-s2.0-33646388655-
dc.type.rimsART-
dc.citation.volume41-
dc.citation.beginningpage1081-
dc.citation.endingpage1091-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/JSSC.2006.872869-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorSohn, JH-
dc.contributor.nonIdAuthorWoo, JH-
dc.contributor.nonIdAuthorLee, MW-
dc.contributor.nonIdAuthorKim, HJ-
dc.contributor.nonIdAuthorWoo, R-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorARM co-processor-
dc.subject.keywordAuthorfixed-point system-
dc.subject.keywordAuthorfrequency scaling-
dc.subject.keywordAuthorlow-power electronics-
dc.subject.keywordAuthormobile applications-
dc.subject.keywordAuthorprogrammability-
dc.subject.keywordAuthorrendering engine-
dc.subject.keywordAuthorsingle-instruction-multiple-data (SIMD) processing-
dc.subject.keywordAuthorthree-dimensional graphics-
dc.subject.keywordAuthorvertex shader-
dc.subject.keywordPlusDECODER-
dc.subject.keywordPlusLSI-
This item is cited by other documents in WoS
⊙ Detail Information in WoSⓡ Click to see webofscience_button
⊙ Cited 28 items in WoS Click to see citing articles in records_button

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0