DC Field | Value | Language |
---|---|---|
dc.contributor.author | Song, SJ | ko |
dc.contributor.author | Park, SM | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2008-07-22T04:49:25Z | - |
dc.date.available | 2008-07-22T04:49:25Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2003-07 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.38, pp.1213 - 1219 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/6246 | - |
dc.description.abstract | A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-mum standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the. ning oscillator. configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and, a folded, differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplisheis the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate. the jitter of the recovered clock to be. 5.2 ps rms and 47 ps pk-pk for 2(31) - 1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10(-6) for 2(31) - 1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | TRANSCEIVER | - |
dc.subject | TECHNOLOGY | - |
dc.title | A 4-gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000183822600016 | - |
dc.identifier.scopusid | 2-s2.0-0038155581 | - |
dc.type.rims | ART | - |
dc.citation.volume | 38 | - |
dc.citation.beginningpage | 1213 | - |
dc.citation.endingpage | 1219 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC32003.813292 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Song, SJ | - |
dc.contributor.nonIdAuthor | Park, SM | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | clock and data recovery | - |
dc.subject.keywordAuthor | CMOS | - |
dc.subject.keywordAuthor | linear phase detector | - |
dc.subject.keywordAuthor | optical receivers | - |
dc.subject.keywordAuthor | voltage-controlled oscillator (VCO) | - |
dc.subject.keywordAuthor | 1/8-rate clock | - |
dc.subject.keywordPlus | TRANSCEIVER | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
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