A 4-gb/s CMOS clock and data recovery circuit using 1/8-rate clock technique

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-mum standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the. ning oscillator. configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and, a folded, differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high common-mode rejection ratio differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplisheis the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate. the jitter of the recovered clock to be. 5.2 ps rms and 47 ps pk-pk for 2(31) - 1 pseudorandom bit sequence (PRBS) input data. The phase noise is measured to be -112 dBc/Hz at 1-MHz offset. The measured bit error rate is less than 10(-6) for 2(31) - 1 PRBS. The chip excluding output buffers dissipates 70 mW from a single 2.5-V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2003-07
Language
ENG
Keywords

TRANSCEIVER; TECHNOLOGY

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.38, pp.1213 - 1219

ISSN
0018-9200
DOI
10.1109/JSSC32003.813292
URI
http://hdl.handle.net/10203/6246
Appears in Collection
EE-Journal Papers(저널논문)
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