A low-power unified arithmetic unit for programmable handheld 3-D graphics systems

A low-power, area-efficient four-way 32-bit multifunction arithmetic unit has been developed for programmable shaders for handheld 3-D graphics systems. It adopts the logarithmic number system (LNS) at the arithmetic core for the single-cycle throughput and the small-size low-power unification of various complicated arithmetic operations such as power, logarithm, trigonometric functions, vector-SIMD multiplication, division, square root and vector dot product. 24-region and 16-region piecewise linear logarithmic and antilogarithmic converters are proposed with 0.8% and 0.02% maximum conversion error, respectively. All the supported operations are implemented with less than 6.3% operation error and unified into a single arithmetic platform with maximum four-cycle latency and single-cycle throughput. A 93 K gate test chip is fabricated using one-poly five-metal 0.18-mu m CMOS technology. It operates at 210 MHz with maximum power consumption of 15.3 mW at 1.8 V.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2007-08
Language
ENG
Keywords

VLSI IMPLEMENTATION; INTERPOLATOR; CONVERTER; PROCESSOR

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.42, pp.1767 - 1778

ISSN
0018-9200
URI
http://hdl.handle.net/10203/6235
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
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