A fully integrated digital hearing aid chip with human factors considerations

A low-power digital hearing aid chip with consideration of the human external ear characteristics according to the each individual user is proposed and implemented. It adopts the pre fitting verification algorithm (PREVA) to obtain the fast and accurate gain fitting and verification in two steps, coarse and fine gain fittings. The ear canal modeling filter circuit (EMC) which models the human external ear into the distributed LC filter enables the coarse gain fitting based on the shape of the external ear of the patient. The fine fitting verification is performed by the external inputs from the hearing loss test results. To reduce the power consumption of the human factored hearing aid chip design, the multi-threshold preamplifier, the adaptive fitting digital signal processor (DSP) with the filter reuse technique and the gated successive approximation ADC are designed and embedded to the digital hearing aid chip. The dynamic range of the multi-threshold preamplifier exists from 0.45 V to 0.8 V and dissipates 32 mu W from a single 0.9 V supply. The fabricated digital hearing aid chip achieves the peak SNR of 81 dB in the overall system with 4.2 mu Vms of input-referred noise voltage. The fabricated chip occupies the core area of 3.12 x 1.20 mm(2) in a 0.18 mu m standard CMOS technology and consumes only 107 mu W from a single 0.9 V supply.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2008-01
Language
ENG
Keywords

HUMAN MIDDLE-EAR; IMPEDANCE

Citation

IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.43, pp.266 - 274

ISSN
0018-9200
URI
http://hdl.handle.net/10203/6233
Appears in Collection
EE-Journal Papers(저널논문)
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