A GAAS JUNCTION-GATE FECFET (J-FECFET) FOR THE DIGITAL INTEGRATED-CIRCUITS

Abstract

We proposed and fabricated a new GaAs Junction-gate floated electron channel FET (J-FECFET) as a unit device for realizing the direct coupled FET logic circuit. By varying the active channel thickness with different mask stripe width in selective MOCVD, we show that the threshold voltages of the fabricated J-FECFET's can be controlled. The enhancement-mode J-FECFET demonstrates the maximum extrinsic transconductance of 350 mS/mm with the threshold voltage of -0.1 V. The depletion-mode J-FECFET's with the higher threshold voltages of -1.67 V and -4.0 V are obtained by reducing the mask stripe width. Negligible sidegate effect is observed in the fabricated J-FECFET.