Power distribution networks for system-on-package: Status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance, for every product generation. In the last decade, high I/O hall grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.
Publisher
Institute of Electrical and Electronics Engineers
Issue Date
2004-05
Language
ENG
Keywords

NOISE; PLANES

Citation

IEEE TRANSACTIONS ON ADVANCED PACKAGING, v.27, no.2, pp.286 - 300

ISSN
1521-3323
DOI
10.1109/TADVP.2004.831897
URI
http://hdl.handle.net/10203/560
Appears in Collection
EE-Journal Papers(저널논문)
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