Design and implementation of efficient FFT processor for OFDM applications = OFDM기반의 효율적인 FFT 설계 및 구현

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Orthogonal Frequency Division Multiplexing (OFDM) has gained considerable attention in recent years. In this paper, we have implemented various FFT architectures on 64-point FFT and present its implementation results. Implementation was processed as two ways. One is HW implementation based on FPGA chip, Xilinx Virtex2 xc2v6000, the other is SW implementation based on DSP chip and ARM core, which is TMS320C6416 and ARM922T. Various FFT architectures are implemented by verilogHDL on xc2v600 Conventional FFT codes and algorithms are coded by C/C++ language on TMS320C64 and ARM922T. The minimum processing times for 64-point FFT were 0.0167 us, 4.58 us and 28.27 us on xc2v6000, TMS320C6416, and ARM922T, respectively. We showed that the criteria point among FPGA, DSP, and ARM in terms of latency, and presented appropriate target devices according to the system timing constraint.
Advisors
Park, Sin-Chongresearcher박신종researcher
Description
한국정보통신대학교 : 공학부,
Publisher
한국정보통신대학교
Issue Date
2005
Identifier
392522/225023 / 020034520
Language
eng
Description

학위논문(석사) - 한국정보통신대학교 : 공학부, 2005, [ vii, 59 p. ]

Keywords

OFDM; FFT; 하드웨어 소프트웨어 구현; HW/SW Implementation; DFT

URI
http://hdl.handle.net/10203/55370
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=392522&flag=dissertation
Appears in Collection
School of Engineering-Theses_Master(공학부 석사논문)
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