An area efficient design and implementation of a 802.11a system

Abstract

Orthogonal Frequency Division Multiplexing (OFDM) has gained considerable attention in recent years. It has been adopted for various standards include the 802.11a wireless LAN standard. In this paper, we implemented an OFDM modem based 802.11a standard. The new architecture of the 802.11a system targeted to reduce the circuit size within decoding latency constraint. High area-efficiency has been achieved by sharing a memory and a multiplier block. Circuit size has been reduced by using a new architecture with the enhanced memory based FFT. The 802.11a designed by using the proposed method uses less number of gates, about 33%, than the one based on the conventional architecture.