CMOS I/Q demodulator design for the IEEE 802.11a direct-conversion receiver = CMOS 공정을 이용한 5.8 GHz IEEE 802.11a 시스템용 direct-conversion 수신기의 I/Q demodulator 설계

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A direct-conversion I/Q demodulator for IEEE 802.11a applications is designed using 0.25-um CMOS process. In this paper, a flicker noise reduction method is suggested. And the average noise figure improvement is larger than 5.7 dB. The principal of this method is to reduce the capacitance at the source node of the switching stages. The designed I/Q demodulator is composed of 2 double-balanced down-conversion mixer and 4 IF buffer. Simulation result show voltage conversion gain = 11.8dB, input-referred 1-dB compression point = -1.2dBm, average noise figure in the signal band = 12dB, input-referred IP2 = +43 dBm respectively, at 3V supply voltage, and 4.2mA current consumption for each mixer. And LO to IF isolation and LO to RF isolation is 66 dB and 88 dB.
Advisors
Yoo, Hyung-Jounresearcher유형준researcher
Description
한국정보통신대학원대학교 : 공학부,
Publisher
한국정보통신대학교
Issue Date
2003
Identifier
392201/225023 / 020013943
Language
eng
Description

학위논문(석사) - 한국정보통신대학원대학교 : 공학부, 2003, [ vi, 43 p. ]

Keywords

Direct-Conversion Receiver; I/Q Demodulator; CMOS; 직접 변환 방식의 수신기; I/Q 복조기; IEEE 802.11a

URI
http://hdl.handle.net/10203/55168
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=392201&flag=dissertation
Appears in Collection
School of Engineering-Theses_Master(공학부 석사논문)
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