In this thesis we present a bandwidth enhancement technique for gigahertz broadband circuitry in CMOS technology. In order to improve bandwidth characteristic of an amplifier, the proposed technique uses multi-level on-chip spiral inductor as shunt-peaking elements. Unlike conventional shunt peaking in which an inductor is used in series with load resistor, this proposed shunt-peaking technique, as named inductance enhanced shunt peaking, gives much higher inductance value at the desired frequency. So, using much smaller on-chip spiral inductor, if the proposed technique is used, shunt-peaking phenomenon that gives an extended bandwidth through pole-zero cancellation can be easily achieved even in the 1-2GHz frequency range. However, On-chip spiral inductor like other passive components consumes a lot of chip area, which is typical of RF IC``s. So, in order to reduce total chip area, in this thesis, multi-level on-chip spiral inductor is used. Multi-level on-chip spiral inductor used for the bandwidth extension adopts a lumped equivalent circuit model of spiral inductor for simple and accurate inductance expressions. For increasing the spacing between inductor and silicon (Si) substrate, resulting in the reduced substrate losses, the used multi-level spiral inductor is implemented without using the lowest metal level. Besides multi-layer metal option, in order to make high Q on-chip spiral inductor, more conductive metallization schem is used.
Finally, the proposed shunt peaking technique is successfully applied to the 2.5Gb/s transimpedance amplifier implemented in $0.35\mum$ CMOS technology. In order to confirm the effects of signal path bandwidth, two different types of transimpedance amplifier are fabricated. These two implementations show about 50mW power dissipation with 3.3V supply. Transimpedance amplifier with a common-source stage achieves 1.45GHz bandwidth with $57dB\Omega$ transimpedance gain and $5.2pA/\surdHz$ input noise current density. And t...