Clock and data recovery circuit for 2.5Gb/s burst-mode optical receiver

Abstract

2.5Gbps burst-mode CDR is newly designed and simulated using ETRI AlGaAs/GaAs HBT with maximum cutoff frequency of 73GHz at collector current 11mA to enable the quick extraction of clock signal from received NRZ burst data and a careful analysis of the results are been followed. This clock recovery scheme is based on matched gated-oscillator and simulation results show that this clock recovery circuit operates up to 2.5Gbps. To form a gated-oscillator, invertors as well as NOR gate are necessary. NOR logic gate with ECL level is newly designed and simulated. Instead of designing new invertor scheme, a wired NOR gate is used as an invertor for the simplicity. MS-DFF is also designed and simulated, which is used for the retiming of the received data stream. MS-DFF is designed with a differential output buffer stage for pulse shaping as well as for driving $50\Omega$ lines. Simulation results showed that this output configuration generates steeper pulses and reduces ripples compared to output emitter-followers, therefore it is appropriate for the case where maximum bit rates are desired. The role of CDR is primarily to synchronize the phase of data with that of recovered clock, and therefore it needs to adapt itself to abrupt frequency variations and sudden phase changes. A typical application of the designed CDR (Clock and Data Recovery) circuit in this paper is a system whose operation relies on instantaneous clock recovery even for NRZ data and in the presence of large and sudden phase changes. This 2.5Gbps high speed CDR circuit presented in this paper can be used in a multi-access packet network such as ATM-PON in which packets may arrive with large amplitude and phase variations.