A PHEMT MMIC LNA with minimized input matching network for 5.8 GHz HiperLAN application5.8 GHz HiperLAN 용 PHEMT 저잡음증폭기 MMIC의 입력정합 최소화 구현

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This thesis describes the design and fabrication of MMIC low noise amplifiers for 5.X GHz wireless LAN applications, using 0.25 $\mum$ gate length AlGaAs/InGaAs/ GaAs pseudomorphic high electron mobility transistors. The two-stage LNA is designed to meet the noise requirements for high data rate wireless LAN, DSRC, and multi-purpose ISM band applications. The first stage of the LNA is designed to provide a simultaneous noise and impedance match by careful adjusting both gate width and series feedback inductance at the source, and the inter-stage and the output stage are matched to $50\Omega$. The on-chip matched LNA has a small signal gain of 16 dB from 5.5 GHz to 8.0 GHz range with a deviation less than $\pm0.4$ dB in its peak to peak values, which shows wide-band gain flatness. Both input and output return losses are less than -10 dB between 5.5 GHz and 8.0 GHz. It reveals noise figure less than 0.88 dB and associated gain over 16 dB at the frequency range between 5.2 GHz and 6.4 GHz. We believe that the noise figure of 0.79 dB at 5.8 GHz is the best result ever reported to date from MMIC LNAs in this frequency range.
Advisors
Park, Chul-Soonresearcher박철순researcher
Description
한국정보통신대학원대학교 : 공학부,
Publisher
한국정보통신대학원대학교
Issue Date
2000
Identifier
392014/225023 / 000993922
Language
eng
Description

학위논문(석사) - 한국정보통신대학원대학교 : 공학부, 2000, [ vii, 59 p. ]

Keywords

MMIC; low noise amplifier; PHEMT; 입력정합 최소화; 저잡음증폭기; minimum matching network; 5.8 GHz

URI
http://hdl.handle.net/10203/54694
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=392014&flag=dissertation
Appears in Collection
School of Engineering-Theses_Master(공학부 석사논문)
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