With the recent proliferation of wireless communication applications, there is an extensive effort to develop low cost, highly integrated RF circuits. In addition, multistandard RF transceivers are desirable to combine two or more standards in on one unit as wireless communication services more diversify. Scaling down of CMOS technologies toward the deep sub-$\mum$ minimum feature size, it may be enable to integrate systems on a chip with having excellent performances.
This research is performed to support the development and implementation of high-linear low-power CMOS low noise amplifier (LNA).
First of all, various noise source, such as the channel thermal noise, the induced gate noise, etc, are studied and the high frequency noise circuit model for the MOSFET is illustrated. And two figure of merits of CMOS LNA circuit performance, noise figure and linearity are discussed.
Next, we analyze the noise characteristics of the principal LNA architecture based on pre-presented noise circuit models of the MOSFET. From these analyses, the CMOS LNA architecture having the capability to have the best noise performance is selected. To design the high-linear LNA with low power consumption, in addition, bias-current re-used technique is adopted.
Finally, to implement dual-band architecture, we combine each output node of LNA for PCS and IMT-2000, respectively, in single output node.
The dual-band CMOS LNA has the following experimental results; a noise figure of 2.93 dB at 1.85 GHz with a forward gain of 11.48 dB (1.85 GHz) and 7.17 dB (2.15 GHz) at power consumption of 18 mW, respectively. And the input IP3 of the amplifier is -0.73 dBm and 1.33 dBm with the input two-tone signal power of -30 dBm and -25 dBm, respectively, with frequency deviation of 5 MHz.
This dual-band LNA is implemented in a standard 0.35$\mum$ CMOS process available through MOSIS.