DC Field | Value | Language |
---|---|---|
dc.contributor.author | Yoo, D | ko |
dc.contributor.author | Park, I | ko |
dc.contributor.author | Maeng, SeungRyoul | ko |
dc.date.accessioned | 2008-06-05T04:59:14Z | - |
dc.date.available | 2008-06-05T04:59:14Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2000-07 | - |
dc.identifier.citation | JOURNAL OF SYSTEMS ARCHITECTURE, v.46, no.9, pp.765 - 778 | - |
dc.identifier.issn | 1383-7621 | - |
dc.identifier.uri | http://hdl.handle.net/10203/4924 | - |
dc.description.abstract | Unidirectional ring-based networks are currently popular choices for high performance large scale shared memory multiprocessors. This class of networks is attractive for their simple hardware interfaces, high speed communication, wider data path, and easy addition of extra nodes. However, a single ring does not scale well due to the fixed bandwidth, and the hierarchical ring networks as a natural extension of a single ring show limited scalability due to their limited bandwidth near the root. In this paper we present a new interconnection network called the Multistage Ring Network (MRN). The MRN has a 2-level hierarchy of rings, and its interconnection of global rings forms a type of the multistage network. The architecture of the MRN is effective at diffusing the global traffic on the network to all global rings, and the bandwidth of the network increases proportionally with increases in the system size. Our results show that in a peak throughput, the MRN performs seven times better than the hierarchical ring network for system size of 1024. (C) 2000 Elsevier Science B.V. All rights reserved. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | ELSEVIER SCIENCE BV | - |
dc.subject | PERFORMANCE EVALUATION | - |
dc.title | Multistage ring network: An interconnection network for large scale shared memory multiprocessors | - |
dc.type | Article | - |
dc.identifier.wosid | 000087464100003 | - |
dc.identifier.scopusid | 2-s2.0-0347074956 | - |
dc.type.rims | ART | - |
dc.citation.volume | 46 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 765 | - |
dc.citation.endingpage | 778 | - |
dc.citation.publicationname | JOURNAL OF SYSTEMS ARCHITECTURE | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Maeng, SeungRyoul | - |
dc.contributor.nonIdAuthor | Yoo, D | - |
dc.contributor.nonIdAuthor | Park, I | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | interconnection network | - |
dc.subject.keywordAuthor | multistage network | - |
dc.subject.keywordAuthor | register insertion ring | - |
dc.subject.keywordAuthor | multiple ring architecture | - |
dc.subject.keywordAuthor | shared memory multiprocessors | - |
dc.subject.keywordPlus | PERFORMANCE EVALUATION | - |
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