Multistage ring network: An interconnection network for large scale shared memory multiprocessors

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dc.contributor.authorYoo, Dko
dc.contributor.authorPark, Iko
dc.contributor.authorMaeng, SeungRyoulko
dc.date.accessioned2008-06-05T04:59:14Z-
dc.date.available2008-06-05T04:59:14Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2000-07-
dc.identifier.citationJOURNAL OF SYSTEMS ARCHITECTURE, v.46, no.9, pp.765 - 778-
dc.identifier.issn1383-7621-
dc.identifier.urihttp://hdl.handle.net/10203/4924-
dc.description.abstractUnidirectional ring-based networks are currently popular choices for high performance large scale shared memory multiprocessors. This class of networks is attractive for their simple hardware interfaces, high speed communication, wider data path, and easy addition of extra nodes. However, a single ring does not scale well due to the fixed bandwidth, and the hierarchical ring networks as a natural extension of a single ring show limited scalability due to their limited bandwidth near the root. In this paper we present a new interconnection network called the Multistage Ring Network (MRN). The MRN has a 2-level hierarchy of rings, and its interconnection of global rings forms a type of the multistage network. The architecture of the MRN is effective at diffusing the global traffic on the network to all global rings, and the bandwidth of the network increases proportionally with increases in the system size. Our results show that in a peak throughput, the MRN performs seven times better than the hierarchical ring network for system size of 1024. (C) 2000 Elsevier Science B.V. All rights reserved.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherELSEVIER SCIENCE BV-
dc.subjectPERFORMANCE EVALUATION-
dc.titleMultistage ring network: An interconnection network for large scale shared memory multiprocessors-
dc.typeArticle-
dc.identifier.wosid000087464100003-
dc.identifier.scopusid2-s2.0-0347074956-
dc.type.rimsART-
dc.citation.volume46-
dc.citation.issue9-
dc.citation.beginningpage765-
dc.citation.endingpage778-
dc.citation.publicationnameJOURNAL OF SYSTEMS ARCHITECTURE-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorMaeng, SeungRyoul-
dc.contributor.nonIdAuthorYoo, D-
dc.contributor.nonIdAuthorPark, I-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorinterconnection network-
dc.subject.keywordAuthormultistage network-
dc.subject.keywordAuthorregister insertion ring-
dc.subject.keywordAuthormultiple ring architecture-
dc.subject.keywordAuthorshared memory multiprocessors-
dc.subject.keywordPlusPERFORMANCE EVALUATION-
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