DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, HC | ko |
dc.contributor.author | Lee, JA | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.date.accessioned | 2007-06-13T07:42:18Z | - |
dc.date.available | 2007-06-13T07:42:18Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.9, no.2, pp.297 - 304 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/488 | - |
dc.description | IEEE Transactions on Very Large Scale Integration Systems | en |
dc.description.abstract | One of the most successful algorithms that bring realism to the world of three-dimensional (3-D) image generation is the Phong shading, With the continuous improvement in VLSI technology and the demand for higher realism, this algorithm is a menable to the commercially available hardware implementation for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However, in this method, the exponentiation of the cosine term requires a very large ROM table, This paper describes the minimization of this overhead in terms of hardware size by proposing an adaptive-compressed nonuniform quantization method. With this method, the ROM table is reduced to 1/64th of the size required for a uniform quantization method while the picture quality is maintained. Due to the reduced ROM table size, the size of the total hardware required for fast Phong shading is minimized to 1/56th of the original size. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A hardware cost minimized fast Phong shader | - |
dc.type | Article | - |
dc.identifier.wosid | 000169035300006 | - |
dc.identifier.scopusid | 2-s2.0-0035301218 | - |
dc.type.rims | ART | - |
dc.citation.volume | 9 | - |
dc.citation.issue | 2 | - |
dc.citation.beginningpage | 297 | - |
dc.citation.endingpage | 304 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | Shin, HC | - |
dc.contributor.nonIdAuthor | Lee, JA | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | adaptive computing | - |
dc.subject.keywordAuthor | computer arithmetic | - |
dc.subject.keywordAuthor | high performance | - |
dc.subject.keywordAuthor | table complexity | - |
dc.subject.keywordAuthor | tradeoffs | - |
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