A hardware cost minimized fast Phong shader

One of the most successful algorithms that bring realism to the world of three-dimensional (3-D) image generation is the Phong shading, With the continuous improvement in VLSI technology and the demand for higher realism, this algorithm is a menable to the commercially available hardware implementation for real-time rendering in 3-D graphics. Taylor series approximation is appropriate for the hardware implementation of fast Phong shading. However, in this method, the exponentiation of the cosine term requires a very large ROM table, This paper describes the minimization of this overhead in terms of hardware size by proposing an adaptive-compressed nonuniform quantization method. With this method, the ROM table is reduced to 1/64th of the size required for a uniform quantization method while the picture quality is maintained. Due to the reduced ROM table size, the size of the total hardware required for fast Phong shading is minimized to 1/56th of the original size.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2001-04
Language
ENG
Description

IEEE Transactions on Very Large Scale Integration Systems

Citation

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.9, no.2, pp.297 - 304

ISSN
1063-8210
URI
http://hdl.handle.net/10203/488
Appears in Collection
EE-Journal Papers(저널논문)
Files in This Item
[TVLSIS2001]hcshin_A Hardware Cost Minimized Fast Phong Shader.pdf(221.46 kB)Download
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