A low-power array multiplier using separated multiplication technique

This brief proposes a separated multiplication technique that can be used in digital image signal processing such as finite impulse response (FIR) filters to reduce the power dissipation. Since the 2-D image data have high spatial redundancy, such that the higher bits of input pixels are hardly changed, the redundant multiplication of higher bits is avoided by separating multiplication into higher and lower parts. The calculated values of the higher bits are stored in memory cells, caches, such that they can be reused when a cache hit occurs. Therefore, the dynamic power is reduced by about 14 % in multipliers by using the proposed separated multiplication technique (SMT) and in a 1-D 4-tap FTR filter by about 10%.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2001-09
Language
ENG
Description

IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing. Sep. 2001.

Citation

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.48, no.9, pp.866 - 871

ISSN
1549-7747
URI
http://hdl.handle.net/10203/487
Appears in Collection
EE-Journal Papers(저널논문)
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