Gate bias induced degradation in hydrogenated amorphous silicon thin film transistors

Abstract

To evaluate the stability of amorphous silicon thin film transistor, thermally stimulated bias stress (TSBS) method is presented. TSBS experiment monitors the drain currents, and the measured drain currents transform into normalized threshold voltage shift. The changes of threshold voltage shift is characterized by two parameters, $E_τ$ and $T_0$, which are related to the effective barrier height and the width of the distribution of barriers for bias induced degradation. The annealing behaviors of the degraded hydrogenated amorphous silicon thin film transistors are studied using isochronal annealing method. We can fit the data using three annealing peaks. And the intensity of the peaks in isochronal annealing spectra changes according to the bias stress conditions (temperature and bias). We can identify three peaks as charge detrapping, interface defect annealing and/or deeply trapped charge detrapping, and defect annealing, respectively. The light induced relaxation phenomena, reduction of threshold voltage and decrease of field effect mobility, are observed in positive bias stressed TFTs. And the gate bias induced enhancement of light induced degradation is also observed. These results can be explained in terms of defect pool model. During the measurement of the temperature dependence of photoconductivity in TFT structure, the photoconductivity thermal quenching is observed for negative gate bias. The type conversion of majority photo carriers is also observed.