DC Field | Value | Language |
---|---|---|
dc.contributor.author | MATSUI, M | ko |
dc.contributor.author | HARA, H | ko |
dc.contributor.author | UETANI, Y | ko |
dc.contributor.author | Kim, Lee-Sup | ko |
dc.contributor.author | NAGAMATSU, T | ko |
dc.contributor.author | WATANABE, Y | ko |
dc.contributor.author | MATSUDA, K | ko |
dc.contributor.author | SAKURAI, T | ko |
dc.date.accessioned | 2007-06-07T01:13:20Z | - |
dc.date.available | 2007-06-07T01:13:20Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1994-12 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.29, no.12, pp.1482 - 1490 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/472 | - |
dc.description | JSSC 1994 | en |
dc.description.abstract | The two-dimensional discrete cosine transform (2-D DCT) has been widely recognized as a key processing unit for image data compression/decompression. In this paper, the implementation of a 200 MHz 13.3 mm(2) 8 x 8 2-D DCT macrocell capable of HDTV rates, based on a direct realization of the DCT, and using distributed arithmetic is presented. The macrocell, fabricated using 0.8 mu m base-rule CMOS technology and 0.5 mu m MOSFET's, performs the DCT processing with 1 sample-(pixel)-per-clock throughput. The fast speed and small area are achieved by a novel sense-amplifying pipeline flip-flop (SA-F/F) circuit technique in combination with nMOS differential logic. The SA-F/F, a class of delay flip-flops, can be used as a differential synchronous sense-amplifier, and can amplify dual-rail inputs with swings lower than 100 mV. A 1.6 ns 20 bit carry skip adder used in the DCT macrocell, which was designed by the same scheme, is also described. The adder is 50% faster and 30% smaller than a conventional CMOS carry look ahead adder, which reduces the macrocell size by 15% compared to a conventional CMOS implementation. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DISCRETE COSINE TRANSFORM | - |
dc.subject | PASS-TRANSISTOR LOGIC | - |
dc.subject | DESIGN | - |
dc.title | A 200-MHZ 13-MM(2) 2-D DCT MACROCELL USING SENSE-AMPLIFYING PIPELINE FLIP-FLOP SCHEME | - |
dc.type | Article | - |
dc.identifier.wosid | A1994PX32100008 | - |
dc.identifier.scopusid | 2-s2.0-0028733304 | - |
dc.type.rims | ART | - |
dc.citation.volume | 29 | - |
dc.citation.issue | 12 | - |
dc.citation.beginningpage | 1482 | - |
dc.citation.endingpage | 1490 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/4.340421 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Kim, Lee-Sup | - |
dc.contributor.nonIdAuthor | MATSUI, M | - |
dc.contributor.nonIdAuthor | HARA, H | - |
dc.contributor.nonIdAuthor | UETANI, Y | - |
dc.contributor.nonIdAuthor | NAGAMATSU, T | - |
dc.contributor.nonIdAuthor | WATANABE, Y | - |
dc.contributor.nonIdAuthor | MATSUDA, K | - |
dc.contributor.nonIdAuthor | SAKURAI, T | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordPlus | DISCRETE COSINE TRANSFORM | - |
dc.subject.keywordPlus | PASS-TRANSISTOR LOGIC | - |
dc.subject.keywordPlus | DESIGN | - |
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