Reducing cache misses through cache line overlapping

By studying the behaviour of general programmes, it was observed that over 50% of bytes in a data cache are zero-valued. To reduce this waste of zero-valued spaces in a data cache, an overlapped cache scheme, which allows one cache line entry to hold up to two cache lines, is proposed. Experimental results show that, for SPEC2000 benchmarks, the proposed design reduces cache misses by 29% on average over a conventional direct-mapped cache.
Publisher
INST ENGINEERING TECHNOLOGY-IET
Issue Date
2006-05
Language
ENG
Citation

ELECTRONICS LETTERS, v.42, no.10, pp.569 - 571

ISSN
0013-5194
DOI
10.1049/el:20064195
URI
http://hdl.handle.net/10203/4686
Appears in Collection
CS-Journal Papers(저널논문)
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