Scheduling a Reentrant Flexible Flow Line for Multi-Chip Package Assembly멀티칩 패키지 조립을 위한 재방문 흐름 공정의 일정계획 방법에 관한 연구

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A multi-chip package (MCP) is assembled by stacking homogeneous or heterogeneous chips into one final package. MCPs can easily increase the circuit density, capacity, and functionality of a package or device without significantly increasing the cost. Therefore, demand on MCPs is rapidly increasing for mobile or digital devices. However, MCP assembly process repeat similar assembly operations as many as the number of chips to be assembled. The assembly machines are shared by the assembly operations for chips of different layers. Furthermore, since some chips are commonly used for different MCP products or different chip layers of a MCP product, the stock of chips should be properly supplied for the assembly operations for each chip layer of each MCP product. The complexity due to reentrant job flows and chip allocation for the assembly operations is further amplified in an MCP assembly line by the large number of similar assembly machines at each assembly process step such as die attach and wire bonding. In this thesis, we consider a unique scheduling problem for an MCP assembly line. To address the complexity, we decompose the scheduling problem into two subproblems, chip stock allocation and machine capacity allocation problems. The chip stock allocation problem should determine how much of the chips of each type in stock should be allocated for lots for different MCP products in different assembly stages so as to meet the daily production requirements of each MCP product. To define the problem, we first develop a mixed integer programming model. A major challenge for solving the problem is with the fact that each lot, even for the same product, has different number of packages. This means that each lot requires different number of chips and individual lots should be considered for scheduling decisions. However, since there are more than several thousands of lots in progress, the complexity of handling individual lots is intractable. We there propose two he...
Advisors
Lee, Tae-Eogresearcher이태억researcher
Description
한국과학기술원 : 산업공학과,
Publisher
한국과학기술원
Issue Date
2008
Identifier
303572/325007  / 020025217
Language
eng
Description

학위논문(박사) - 한국과학기술원 : 산업공학과, 2008. 8., [ vii, 89 p. ]

Keywords

multip-chip package; reentrant; assembly; parallel machines; scheduling; 멀티칩 패키지; 재방문; 조립; 병렬설비; 일정계획; multip-chip package; reentrant; assembly; parallel machines; scheduling; 멀티칩 패키지; 재방문; 조립; 병렬설비; 일정계획

URI
http://hdl.handle.net/10203/40634
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=303572&flag=dissertation
Appears in Collection
IE-Theses_Ph.D.(박사논문)
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