DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Park, Song-Bai | - |
dc.contributor.advisor | 박송배 | - |
dc.contributor.author | Lee, Jae-Cheol | - |
dc.contributor.author | 이재철 | - |
dc.date.accessioned | 2011-12-14T02:21:03Z | - |
dc.date.available | 2011-12-14T02:21:03Z | - |
dc.date.issued | 1982 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=63397&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/39592 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1982.2, [ 1책(면수복잡) ] | - |
dc.description.abstract | Recently, switch-level model emerges to describe the logical behavior of digital integrated circuits implemented by MOS technology. Since in the switch-level model MOS transisters are primitive elements which consist of logic networks, a simulator which has switch-level model as its basis shows generality and accuracy in simulating MOS logic networks. In this thesis, a switch-level model of MOS logic networks is presented, which can cover almost all MOS structures. A switch-level logic simulator named KAISIM based on this model is developed. Some example circuits are simulated with KAISIM, which show accurate results. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | MOS logic network simulation with a swithch-level model | - |
dc.title.alternative | 스위치 레벨 모델을 이용한 MOS 논리 회로망의 시뮬레이션 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 63397/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 000801211 | - |
dc.contributor.localauthor | Park, Song-Bai | - |
dc.contributor.localauthor | 박송배 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.