MOS logic network simulation with a swithch-level model = 스위치 레벨 모델을 이용한 MOS 논리 회로망의 시뮬레이션

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Recently, switch-level model emerges to describe the logical behavior of digital integrated circuits implemented by MOS technology. Since in the switch-level model MOS transisters are primitive elements which consist of logic networks, a simulator which has switch-level model as its basis shows generality and accuracy in simulating MOS logic networks. In this thesis, a switch-level model of MOS logic networks is presented, which can cover almost all MOS structures. A switch-level logic simulator named KAISIM based on this model is developed. Some example circuits are simulated with KAISIM, which show accurate results.
Advisors
Park, Song-Bairesearcher박송배researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1982
Identifier
63397/325007 / 000801211
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1982.2, [ 1책(면수복잡) ]

URI
http://hdl.handle.net/10203/39592
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=63397&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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