(The) effect of process parameter variation on the performance of MOS linear integrated circuit = Process parameter 의 변화가 MOS 선형집적 회로의 성능에 미치는 영향

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dc.contributor.advisorKim, Choong-Ki-
dc.contributor.advisor김충기-
dc.contributor.authorShin, Jang-Kyoo-
dc.contributor.author신장규-
dc.date.accessioned2011-12-14T02:19:57Z-
dc.date.available2011-12-14T02:19:57Z-
dc.date.issued1980-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=62705&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/39519-
dc.description학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1980.2, [ [ii], 68, [2] p. ]-
dc.description.abstractThe importance of implementing analog circuit functions in MOS/LSI has recently been recognized. The performance of MOS linear integrated circuit is governed by the process parameters such as threshold voltage ($V_T$), junction depth($X_J$), and gate oxide thickness($T_{OX}$). In this thesis, discrete MOS transistors with different(Z/L)``s are fabricated using standard p-MOS process and the process parameters are measured. An integrated p-MOS amplifier with external compensation is designed to study the effect of measured process parameter variation on the circuit performance such as voltage gain ($A_V$), input offset voltage, cutoff frequency($f_T$), and common mode rejection ratio(CMRR) using simulation program MSINC.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.title(The) effect of process parameter variation on the performance of MOS linear integrated circuit = Process parameter 의 변화가 MOS 선형집적 회로의 성능에 미치는 영향-
dc.typeThesis(Master)-
dc.identifier.CNRN62705/325007-
dc.description.department한국과학기술원 : 전기 및 전자공학과, -
dc.identifier.uid000781114-
dc.contributor.localauthorKim, Choong-Ki-
dc.contributor.localauthor김충기-
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EE-Theses_Master(석사논문)
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