DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kim, Choong-Ki | - |
dc.contributor.advisor | 김충기 | - |
dc.contributor.author | Shin, Jang-Kyoo | - |
dc.contributor.author | 신장규 | - |
dc.date.accessioned | 2011-12-14T02:19:57Z | - |
dc.date.available | 2011-12-14T02:19:57Z | - |
dc.date.issued | 1980 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=62705&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/39519 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1980.2, [ [ii], 68, [2] p. ] | - |
dc.description.abstract | The importance of implementing analog circuit functions in MOS/LSI has recently been recognized. The performance of MOS linear integrated circuit is governed by the process parameters such as threshold voltage ($V_T$), junction depth($X_J$), and gate oxide thickness($T_{OX}$). In this thesis, discrete MOS transistors with different(Z/L)``s are fabricated using standard p-MOS process and the process parameters are measured. An integrated p-MOS amplifier with external compensation is designed to study the effect of measured process parameter variation on the circuit performance such as voltage gain ($A_V$), input offset voltage, cutoff frequency($f_T$), and common mode rejection ratio(CMRR) using simulation program MSINC. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | (The) effect of process parameter variation on the performance of MOS linear integrated circuit | - |
dc.title.alternative | Process parameter 의 변화가 MOS 선형집적 회로의 성능에 미치는 영향 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 62705/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 000781114 | - |
dc.contributor.localauthor | Kim, Choong-Ki | - |
dc.contributor.localauthor | 김충기 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.