Nowadays there has been much effort to increase the performance of computer system. Along with rapid progress in semiconductor technology, high speed and low cost central processing unit has been developed. But there are many problems in connecting such high performance CPU to the real world. All the mechanical parts which are required cannot match the speed inherent in electronic processing. The whole system performance thus has to be limited according to their I/O performance. Many attempts have been made and the multiprocessor architecture is proposed as one kind of solutions. In this thesis, I/O processor Interface is designed and implemented in order to provide high I/O data rates and I/O capacity of wide variety on small machines by using shared memory and some flags and to do so, computer architecture, interprocess timing, and softtest method must be studied.