Hardware implementation of the programmable IIR digital filter with one high speed multiplier

Abstract

The programmable infinite impulse response digital filter with parallel data structure is designed and its hardware is implemented by using digital IC``s. One outstandign feature of the digital filter designed in this thesis is that only one high speed paralled-paralled multiplier is used to realize the basic canonical second-order digital filter and that the order of digital filter can be varied by adjusting the control circuit, i.e., input terminals of this digital filter system are multiplexed to achieve different filter orders. The performance test is carried out on the hardwired programmable digital filter from various viewpoints and some problems that occasionally occur in digital signal processing are studied during the test. After the design is completed, the system simulation is performed on the level of functional blocks by digital computer in order to verify its operation.