Mask layout generation using symbolic layout approach = Symbolic layout approach를 이용한 mask layout 의 제작

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Among several methodologies developed for designing the mask layout of IC, symbolic layout approach reduces the design cycle and minimizes the design costs by alleviating the attention to be paid to keept up the design rules in layout generation. In this thesis, a Symbolic layou T EDItor called STEDI and a COmpAcTor called COAT are introduced. While STEDI, which is an interactive editing system implemented in IBM-PC with NOVA*GKS as graphics routines, produces the symbolic layout in ICDL(Intermediate Circuit Description Languages), COAT inputs ICDL data and generates the corresponding compacted mask layout in CIF(Caltech Intermediate Form). COAT solves the constraint graph with mixed constraints.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
1987
Identifier
65799/325007 / 000841290
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1987.8, [ [iii], 59 p. ]

URI
http://hdl.handle.net/10203/39064
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=65799&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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