Design of high speed CMOS Pipeline A/D converter

Abstract

A high speed CMOS pipeling A/D converter has been developed, wherein arrayed precision-matched 1 bit algorithmic A/D conversion cells operate in pipeline processing, and a first order cancellation of the charge injection effect from MOS transistor switches is attained with a combination of differential circuit implementation and an optimum timing scheme. Single-stage fully-differential cascode amplifiers and comparators are extensively used to attain high speed conversion. The prototype circuit show 8bit A/D conversion at 10MHz sampling rate. Performances of the pipeling A/D converter are studied by computer simulation and the layout of a test chip has been implemented using 3-um single-silicon gate p-well CMOS process.