Rule-based compaction of symbolic layout

Abstract

This thesis describes a rule-based compaction system for automatically compacting the symbolic layout of integrated circuit for CMOS cells. The compactor accomplishes the compaction task by augmenting some algorithmic technique with the domain specific knowledge encoded as rules. There is a new compaction strategy which uses concepts of virtual grid, group and preferred patterns in order to compact the loosely specified topology with an automatic jog insertion. The compaction algorithm of using such concepts is both simple and fast and can insert the jog effectively. The system is implemented in EOPS5 that is the extended version of OPS5, a general purpose rule-based language.