Investigation on multi-level-cell NVM in unified-RAM (URAM)

Abstract

Unified random access memory (URAM)─functioning 2-bit non-volatile flash memory and a capacitorless 1T-DRAM in a single transistor─is presented based on a partially-depleted (PD) SONOS FinFET and a PD SOI structure. A PD SONOS FinFET performs capacitorless 1T-DRAM in a high speed mode with a program/erase (P/E) of 50nsec as well as 2-bit-multi-level cell (MLC) NVM in a non-volatile mode with data retention of 10 years by using Fowler-Nordheim tunneling and hot carrier injection (HCI) mechanism. In order to prevent soft- program issue for 1T-DRAM, the underlap architecture between gate and junction is suggested in PD SONOS SOI structure as compared with overlap architecture. The fabricated underlap and overlap devices in PD SONOS SOI show characteristics of soft-program immunity and dual-bit NVM as threshold voltage read method and GIDL read method.