(A) digital phase-locked loop with phase detector quantization noise suppression techniques위상차 검출기의 양자화 잡음을 줄이는 방법을 사용한 디지털 위상고정루프

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dc.contributor.advisorCho, Seong-Hwan-
dc.contributor.advisor조성환-
dc.contributor.authorSon, Woo-Kon-
dc.contributor.author손우곤-
dc.date.accessioned2011-12-14T02:07:44Z-
dc.date.available2011-12-14T02:07:44Z-
dc.date.issued2009-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=308820&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/38700-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2009.2, [ vii, 49 p. ]-
dc.description.abstractThis thesis presents a phase detector (PD) quantization noise suppression techniques for low-noise digital phase-locked loops (DPLLs). Unlike conventional DPLLs that require high resolution time-to-digital convertors (TDCs), the proposed DPLL achieves a low-noise performance without it. First is the proportional path in the proposed DPLL is removed in order to suppress the quantization noise of the phase detector (PD). Instead, a zero is added by a sub-feedback loop around the reference phase accumulator to maintain the stability of the loop. Second is sigma-delta modulation (SDM) of division value to reduce spurious tones induced by limited resolution of a TDC. The proposed techniques do not require any precise analog or time domain circuits such as a TDC and hence can be fully synthesized without any calibration. As a result, the noise performance of the proposed DPLL is significantly improved. The proposed DPLL is theoretically analyzed and simulated in CppSim, a time-domain simulator, which shows in-band noise improvement of 10dB at in-band frequency offset. In addition, a prototype chip is implemented in 65nm CMOS process in order to verify the proposed techniques. The prototype achieves -78dBc/Hz at 10kHz offset for a 3-GHz output while dissipating 16.7mW and occupying an area of $0.16 mm^2$.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectdigital phase-locked loops (DPLLs)-
dc.subjectquantization noise-
dc.subjecttime-to-digital converter (TDC)-
dc.subjectdigitally-controlled oscillator (DCO)-
dc.subjectmodeling-
dc.subject디지털 위상고정루프-
dc.subject양자화 잡음-
dc.subject시간-디지털 변환기-
dc.subject디지털 제어 발진기-
dc.subject모델링-
dc.subjectdigital phase-locked loops (DPLLs)-
dc.subjectquantization noise-
dc.subjecttime-to-digital converter (TDC)-
dc.subjectdigitally-controlled oscillator (DCO)-
dc.subjectmodeling-
dc.subject디지털 위상고정루프-
dc.subject양자화 잡음-
dc.subject시간-디지털 변환기-
dc.subject디지털 제어 발진기-
dc.subject모델링-
dc.title(A) digital phase-locked loop with phase detector quantization noise suppression techniques-
dc.title.alternative위상차 검출기의 양자화 잡음을 줄이는 방법을 사용한 디지털 위상고정루프-
dc.typeThesis(Master)-
dc.identifier.CNRN308820/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020073257-
dc.contributor.localauthorCho, Seong-Hwan-
dc.contributor.localauthor조성환-
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EE-Theses_Master(석사논문)
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