The output driver with constant slew-rate and duty cycle against PVT variationsPVT 변화에 일정한 Slew-rate과 Duty cycle을 갖는 Output Driver

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 923
  • Download : 0
DC FieldValueLanguage
dc.contributor.advisorKim, Lee-Sup-
dc.contributor.advisor김이섭-
dc.contributor.authorShin, Seung-Jun-
dc.contributor.author신승준-
dc.date.accessioned2011-12-14T02:06:56Z-
dc.date.available2011-12-14T02:06:56Z-
dc.date.issued2008-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=301989&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/38648-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2008. 8., [ v, 43 p. ]-
dc.description.abstractThe speed of Dram has been increased rapidly with the development of various multi-media applications. It is important that data is transfered and received without the distortion of the one in high speed interface. The object of this research is the slew rate control of output driver using in Dram. To transfer data in Gb/s interface, it has to be considered that the factor, which is like as PVT variation, I/O component capacitance reduces the data margin. Because, slew rate is varied over these factors. High slew rate of output driver makes low noise margin due to SSO noise (Simultaneous-Switching Output noise). Low slew rate reduces data eye and leads to ISI (Inter-Symbol Interference). Above two cases lead to reduce data margin. So if slew-rate is changed sensitively by a certain variable, output driver can’t transfer the data stably. This is the reason that slew rate has to be constant and moderated for high speed output driver in PVT, I/O capacitance variation. Many researches about slew rate control over PVT variation have performed. There are several methods like that compensation using PLL[1], compensation using replica bias circuit[2], compensation using capacitive feedback[3]. But the compensation method using capacitive feedback is not suitable for Gb/s interface, because the circuit for detecting PVT environment is not existed. whenever each rising and falling edge of data is occurred, the compensation process has to be followed. So it makes limitation to reduce compensation time. The compensation method using PLL is difficult to apply to dram output driver which is formed of coded driver. Because slew rate control circuit has large area. Output driver is composed of main driver, pre-driver. Generally, Pre-driver controls the slew rate. Turning on and off the PMOS and NMOS gate of main driver using pre-driver, the slew and driving strength of main driver is adjusted. This research is on this basic. Conventional slew rate controlled output dr...eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectPVT-
dc.subjectslew rate-
dc.subjectdriver-
dc.subject피브이티-
dc.subject슬루레이트-
dc.subject드라이버-
dc.subjectPVT-
dc.subjectslew rate-
dc.subjectdriver-
dc.subject피브이티-
dc.subject슬루레이트-
dc.subject드라이버-
dc.titleThe output driver with constant slew-rate and duty cycle against PVT variations-
dc.title.alternativePVT 변화에 일정한 Slew-rate과 Duty cycle을 갖는 Output Driver-
dc.typeThesis(Master)-
dc.identifier.CNRN301989/325007 -
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020063283-
dc.contributor.localauthorKim, Lee-Sup-
dc.contributor.localauthor김이섭-
Appears in Collection
EE-Theses_Master(석사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0