(A) low phase-noise frequency synthesizer using two phase-locked-loops

Abstract

This paper presents two architectures which improve the phase-noise performance of frequency synthesizer. Both two architectures are designed to reduce the quantization noise from delta-sigma modulator(DSM) and they consist of two simple PLLs, thereby reducing the design complexities which come from digital control circuits. One of them, which is based on OPLL, is implemented in 0:25¹m process and it shows the comparable performance to that of previous works. Moreover it consumes less power. The other architecture is based on Nested-PLL architecture. This architecture has some stability problem which is not generally found in conventional ??-§ fractional-N PLL. The proposed architecture eliminates the design considerations because the one of the PLL is operated at low-frequency. Hence the proposed architecture can consume less power than ??rst proposed architecture which is based on OPLL and it could occupy smaller area since the low-frequency VCO can be designed as the ring-type. The simulation results of second proposed architecture shows that the proposed architecture has a good phase-noise reduction performance.