State retention architecture exploration for power gating

Abstract

As power gated block cannot preserve the states of latch and flip-flop, it needs state retention method for power gating. Mostly, designers use retention flip-flop, which generates large area overhead and leakage power consumption. In this paper, we propose state retention architecture exploration algorithm which minimizes area overhead and energy consumption. This architecture is based on scan-based retention (use scan-chain and SRAM), and this algorithm indicates number of parallel scan-chains and word size of SRAM that minimize energy consumption. For implementing this architecture, we present novel scan-chain scheme which can use multiple scan-chains irrelevant to limitation on number of pins in chip. Finally, we present a technique to reduce area overhead through sharing SRAM without increasing energy consumption. Comparing with using retention flip-flop, our state retention architecture has 13% area reduction and 28% energy reduction about H.264 decoder with TSMC 65nm technology library [1].