State retention architecture exploration for power gating = 파워 게이팅을 위한 데이터 저장 구조 탐색

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As power gated block cannot preserve the states of latch and flip-flop, it needs state retention method for power gating. Mostly, designers use retention flip-flop, which generates large area overhead and leakage power consumption. In this paper, we propose state retention architecture exploration algorithm which minimizes area overhead and energy consumption. This architecture is based on scan-based retention (use scan-chain and SRAM), and this algorithm indicates number of parallel scan-chains and word size of SRAM that minimize energy consumption. For implementing this architecture, we present novel scan-chain scheme which can use multiple scan-chains irrelevant to limitation on number of pins in chip. Finally, we present a technique to reduce area overhead through sharing SRAM without increasing energy consumption. Comparing with using retention flip-flop, our state retention architecture has 13% area reduction and 28% energy reduction about H.264 decoder with TSMC 65nm technology library [1].
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2008
Identifier
297162/325007  / 020063118
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2008.2, [ vi, 38 p. ]

Keywords

power gating; leakage power; sleep transistor; state retention; low power; 파워 게이팅; 데이터 저장 구조; 저전력; power gating; leakage power; sleep transistor; state retention; low power; 파워 게이팅; 데이터 저장 구조; 저전력

URI
http://hdl.handle.net/10203/38545
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=297162&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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