Cache miss aware dynamic stack allocation = 캐쉬 미스를 고려한 동적 스택 할당

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Reducing cache misses without increasing cache associativity is critical for reducing the power consumption and cache access time. This paper has focused on the stack of a program which often occupies more than half of total memory accesses. This paper, as a result, proposes so-called dynamic stack allocation where the stack pointer is shifted at run time to a memory location which is expected to cause least number of cache misses. We implemented the proposed scheme using so-called Dynamic Stack Allocator(DSA) which consists of Cache Miss Predictor(CMP) to compute cache miss probability based on Least Recently Used(LRU) policy and Stack Pointer Manger(SPM) to manage multiple stack locations. We also verified the proposed scheme with both FPGA and ASIC by using iNCITE and Dong-Bu electronics 0.18um process, respectively. Experimental results show that dynamic stack allocation significantly reduces cache misses from 1% to 42% in various benchmarks with relatively small power consumption and no extra delay.
Advisors
Kyung, Chong-Minresearcher경종민researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2007
Identifier
265001/325007  / 020053518
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2007.2, [ vi, 47 p. ]

Keywords

Stack; Cache miss; Dynamic stack allocator; 동적 스택 할당기; 스택; 캐쉬 미스

URI
http://hdl.handle.net/10203/38490
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=265001&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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