Skewed flip-flop transformation for minimizing leakage in sequential circuits순차 회로의 누설 전류를 줄이기 위한 비대칭 플립 플롭 변환

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Mixed $V_t$ has been widely used to control leakage without affecting circuit performance. However, current approaches target the combinational circuits even though sequential elements, such as flip-flops, contribute an appreciable proportion of the total leakage. A skewed flip-flop (SFF) is obtained by slightly increasing the gate length of a subset of the transistors in a conventional flip-flop. The resulting SFF will exhibit very skewed characteristics in terms of leakage and delay, which depend on the transistors that are replaced. We present an algorithm that selectively substitutes SFFs for conventional flip-flops in sequential circuits, such that the timing constraint is still satisfied while the leakage from the flip-flops is reduced. When combined with the mixed Vt technique, an average leakage saving of 17% is achieved, compared to the use of mixed $V_t$ alone. The leakage of the flip-flops themselves is cut by 56% on average.
Advisors
Shin, Young-Sooresearcher신영수researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2007
Identifier
264969/325007  / 020053266
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2007.2, [ vi, 48 p. ]

Keywords

leakage current; sequential circuit; Flip-flop; low power; 저전력; 누설 전류; 순차 회로; 플립 플롭; mixed Vt

URI
http://hdl.handle.net/10203/38461
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=264969&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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