(A) low power hybrid adder using single-stage multiplexer circuits

Abstract

The adder is the most important arithmetic component that it is commonly used in microprocessors and mobile devices. As the mobile systems get popular recently, the concern over the high performance and low power adder gets larger than before. By this time, the research about the adder has been well advanced, and the hybrid adder technique to satisfy simultaneously high performance operation, low power consumption and cost effectiveness was frequently used. Above-mentioned hybrid adder is the adder implemented using merits of some adders. On the one hand, the current digital logic design trend is toward the static logic having the merit of being robust in the presence of noise because the dynamic logic has the parasitic effects such as charge sharing and charge leakage. There are some hybrid adders composed of the static logic. They are implemented to Ling’s derivation and conditional sum architecture. In these adders, the part generating the carry signal is optimized, but the part outputting the final sum is complex and composed of lots of transistors. Therefore, the load capacitance connected to carry signals and the parasitic capacitance between transistors is large. So, the transistors of larger size are required in gates connected to the large load capacitance. This method contents the high performance operation, but it does not content the low power consumption. To solve this problem, the new conditional sum architecture-I and the new conditional sum architecture-II of the simple structure is proposed in this thesis, where they are composed of not two-stage multiplexer circuits but single-stage multiplexer circuits. In the proposed conditional sum architecture, the control signal of the conventional conditional sum architecture is used as input signals of a logic gate, and the output signal of one is used as the control signal of single-stage multiplexer circuits. Then, the load capacitance and parasitic capacitance in conditional sum architecture is r...