Network processor performance analysis

Abstract

Fast changing network applications and evolving network processor NP architecture coping to provide the required demand of these application has made NP software developers task more difficult than ever. We redefine the NP benchmark for standard network applications targeting the processing resource sought by these applications thus reducing the programming overhead and modular applications allocation complexity over multiple microengines or processing elements. Moreover, two different paradigm on packet processing is represented with four typical header processing applications and one payload processing application. The model extracts spectrum of data ranging from micro level parameter to macro level. Advantage of having two level of analysis completes performance genome as variation in processing elements on throughput, a macro level parameter, is well correlated with its corresponding micro level parameter such as Instruction per Cycle (IPC), energy per cycle and instructions per second. These parameters are obtained for each building blocks of a programmable router, thereby giving atomic level information of NP for the building blocks considering processing variation. Instruction Processing Rate (million instructions per second MIPS) with Execution Cycle EC are two measures quantifying processing resource requirement and efficiency of the microengine while running on specific number of threads and microengines. The presented results help understand on optimal configuration of processing capacity of NP for resource intensive program kernel. The processing requirement of each benchmark application module assist in NP based power management and power efficient processing resource allocation for typical network applications.