Performance-optimized synthesis of finite temporal property for functional coverage in co-emulation system

Abstract

Functional verification has emerged as the dominant bottleneck of the design process in recent industry. Functional coverage is the most critical measure of thoroughness for the verification of a complex design. It reduces the verification time by contributing to removing redundant test vectors and obtaining optimal test suite. But the functional coverage requires much computational power and slows down the verification process. This thesis proposes a hardware unit for functional coverage which contributes to the acceleration of functional coverage. Furthermore, it allows the functional coverage to be run with co-emulation system. In this thesis, we propose a method to synthesize monitors for a coverage model that is composed of finite temporal properties. Proposed synthesizable monitors, coverage monitors, check functional coverage in the co-emulation system. Coverage monitors utilize the power of co-emulation system and give more improvement to the verification team with the acceleration of the design. Coverage monitors provide over hundred times higher performance than software-based functional coverage and get rid of limitations posed by software-based functional coverage tools. Performance optimization method for the storing results in block RAM of the FPGA is also proposed. In transaction-level co-emulation, coverage monitors keep records of occurrences of properties in the FPGA because one transaction advances hundreds clocks of the design. The proposed memory binding algorithm which considers the compatibility and conflict among different properties also help to reduce the slowdown by storing results.