Microwave frequency model of wafer level package based on s-parameter measurement = S-파라미터 측정을 통한 마이크로파 영역에서의 Wafer Level Package 모델에 관한 연구

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In this paper, we firstly present the high frequency equivalent circuit model of Wafer Level Package (WLP) interconnection up to 5 GHz. Since WLP interconnection is fabricated on the semiconductor, it can be compared with on-chip MIS transmission lines. But the dimension of the WLP interconnection, such as thickness of dielectric layer and metal line, is much larger than that of the on-chip interconnection. Previous studies about MIS structure cannot be applied directly to WLP interconnection. The thick dielectric layer and on-chip metal plane in the WLP interconnection result in relatively low slow wave factor. Measurement results, along with the quite low loss, confirm operation in a quasi-TEM mode in the WLP interconnection. The extracted model parameters from measured S-parameters are compared with theoretical results on several such structures. Excellent agreement is found, which shows WLP interconnection can be regarded as conductor-backed coplanar waveguide with silicon losses. Finally, based on the extracted model parameters, we simulated the signal integrity of Rambus Memory Module when WLP is applied. And successfully demonstrated that the increased capacitive loading of WLP can be compensated by choosing proper line impedance.
Advisors
Kim, Joung-Horesearcher김정호researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2001
Identifier
169420/325007 / 000993430
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ v, 50 p. ]

Keywords

S-parameter measurement; Wafer Level Package; Model; 모델; S-파라미터 측정; 웨이퍼 수준 패키지

URI
http://hdl.handle.net/10203/37488
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169420&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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