RTL design verification with target H/W

Abstract

As a result of shorter design cycle time and increasing complexity, the verification of VLSI systems at the early stage of development is becoming more important. Conventional design verification methods, simulation and emulation has shortcomings in test vector generation and in debugging. As a result, they have been used complementarily to make up for each other. I present new design verification method that picks out merits of the two method: easy debugging and no need for test vector generation. In this method the design is divided into core logic and interface logic. The former is simulated in the software part of the virtual chip emulation system and the latter is mapped in the hardware part of the system. The software part and hardware part is connected by the system bus of the virtual chip emulation system and the simulator accesses the hardware part by the system task function. By simply calling appropriate system task function, the core model can communicate with the interface logic. This verification mechanism is checked by applying it to mp3 decoder chip model.