100BaseT4 이더넷 송수신기를 위한 타이밍 복원 회로의 설계Timing recovery circuit design for 100BaseT4 ethernet transceiver
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 김범섭 | - |
| dc.contributor.advisor | Kim, Beom-Sup | - |
| dc.contributor.author | 이준석 | - |
| dc.contributor.author | Lee, Joon-Suk | - |
| dc.date.accessioned | 2011-12-14T01:40:22Z | - |
| dc.date.available | 2011-12-14T01:40:22Z | - |
| dc.date.issued | 1997 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=114245&flag=dissertation | - |
| dc.identifier.uri | http://hdl.handle.net/10203/36945 | - |
| dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1997.2, [ v, 52 p. ] | - |
| dc.language | kor | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | 디지탈 PLL | - |
| dc.subject | 이더넷 송수신기 | - |
| dc.subject | 타이밍 복원 | - |
| dc.subject | PLL | - |
| dc.subject | DPLL | - |
| dc.subject | Timing recovery | - |
| dc.subject | Ethernet | - |
| dc.subject | 100BaseT4 | - |
| dc.title | 100BaseT4 이더넷 송수신기를 위한 타이밍 복원 회로의 설계 | - |
| dc.title.alternative | Timing recovery circuit design for 100BaseT4 ethernet transceiver | - |
| dc.type | Thesis(Master) | - |
| dc.identifier.CNRN | 114245/325007 | - |
| dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
| dc.identifier.uid | 000953476 | - |
| dc.contributor.localauthor | 김범섭 | - |
| dc.contributor.localauthor | Kim, Beom-Sup | - |
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- EE-Theses_Master(석사논문)
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