VLIW 프로세서를 위한 부동 소수점 유닛의 설계A design of floating-point unit for VLIW processor

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dc.contributor.advisor경종민-
dc.contributor.advisorKyung, Chong-Min-
dc.contributor.author류창호-
dc.contributor.authorRyu, Chang-Ho-
dc.date.accessioned2011-12-14T01:39:53Z-
dc.date.available2011-12-14T01:39:53Z-
dc.date.issued1997-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=114210&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36914-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1997.2, [ vi, 55, 2 p. ]-
dc.languagekor-
dc.publisher한국과학기술원-
dc.subject부동 소수점-
dc.subject분리 수행-
dc.subjectSplittable operation-
dc.subjectFloating-point-
dc.titleVLIW 프로세서를 위한 부동 소수점 유닛의 설계-
dc.title.alternativeA design of floating-point unit for VLIW processor-
dc.typeThesis(Master)-
dc.identifier.CNRN114210/325007-
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid000953183-
dc.contributor.localauthor경종민-
dc.contributor.localauthorKyung, Chong-Min-
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EE-Theses_Master(석사논문)
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