High performance cache design for superscalar microprocessor

Abstract

This paper suggests several control schemes with a high performance on-chip cache design which would be incorporated with a superscalar microprocessor, pin-to-pin compatible to Intel``s $\mbox{Pentium}^{TM}$ processor. The on-chip cache, PCache, designed as a basis of all works in this paper, is characterized as a separate cache architecture embarking even/odd divided tags. The cache realizes superscalar supports using multi-port for tag and interleaved RAM for relatively large data RAM. Employing a smart separate controller, the proposed schemes were focused on reducing miss rate and miss penalty rather than increasing the circuit speed upon which previous works concentrated chiefly. Write forwarding of fill buffer and modified pseudo LRU schemes diminish miss rates, and active empty slot allocation decreases miss penalty. Simulation results that verify the potential effectiveness of each control scheme also assure that the proposed schemes jointly improve the performance of the system significantly. This fact illuminates a speculative cache control``s importance on the full system performance.