Power-efficient 2-step algorithm and structure for Chien search

Abstract

Chien Search algorithm is a one of the BCH code decoding algorithm and it is used to find the error-location in the received signal from the error-location polynomial. Chien Search algorithm has been implemented in hardware, but its structure is iterative and has a lot of power consumption when the code length is getting longer or the architecture selects much more parallel structure. In this thesis, to improve the power consumption of conventional Chien Search architecture and keep the high throughput, new Chien Search architecture - power-efficient 2-step Chien Search is proposed and implemented. Let the Chien Search structure check the low-part of the output. If the low-bit of output is same as 1, there is possibility of finding the error. If not, there exists absolutely no error. By separating the Chien Search algorithm to 2-step, early detection of ‘not the error’ is available and if ‘not the error’ is determined, $2^{nd}$ step is bypassed and power saving is achieved. Furthermore, to save the power consumption more, the $2^{nd}$ stage is converted to the conventional iterative structure. The iterative structure has less gates than parallel one, so the power saving can be achieved. Even the throughput can be little bit lost, the number of access to $2^{nd}$ stage also can be reduced by increasing the check-bit of $1^{st}$ stage. So throughput loss would be smaller. The implementation results is that with 0.13-μm CMOS technology working frequency is 200 MHz and power consumption improvement is maximally 35 % better than conventional parallel Chien Search architecture for full-parallel architecture, 50% better for serial-parallel hybrid architecture.