Retiming pulsed-latch circuits for high-performance ASIC designs고성능 ASIC 디자인을 위한 펄스 래치 회로 리타이밍 기법

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Pulsed-latches take advantage of both latches in their high performance and flip-flops in their convenience of timing analysis. To minimize the clock period of pulsed-latch circuits for a higher performance, a problem of combined retiming and time borrowing is formulated, where the latter is enabled by using a handful of different pulse widths. The problem is first approached by formulating it as an integer linear programming to lay a theoretical foundation. A heuristic approach is proposed, which solves the problem by conceptually performing clock skew scheduling for the minimum clock period and gradually converting skew into a combination of retiming and time borrowing. Experiments with 45-nm technology demonstrate that the clock period is improved for all benchmark circuits with an average of 13% with less use of extra latches compared to the conventional retiming.
Advisors
Shin, Young-Sooresearcher신영수researcher
Description
한국과학기술원 : 전기 및 전자공학과,
Publisher
한국과학기술원
Issue Date
2010
Identifier
419290/325007  / 020083372
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 2010.2, [ vii. 43 p. ]

Keywords

Retiming; Fast ASIC; Pulsed-Latch; 펄스 래치; 리타이밍; 고성능 ASIC

URI
http://hdl.handle.net/10203/36649
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=419290&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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