Modeling and analysis of noise coupling and RF sensitivity in through-silicon-via (TSV) silicon interposer

Abstract

As the convergence of various functions in a single electronic system drives current technical trends, the interconnection density has been significantly increasing. To keep up with the industrial need which requires higher performance and smaller form factor at the same time, three dimensional (3D) IC has been considered very promising technology. One of the most integral technologies for realization of 3D IC is Through-Silicon-Via (TSV) silicon interposer. Through Silicon Via is essential to vertically connect silicon substrate instead of wire-bonding with shorter interconnection length. Silicon interposer is a kind of carrier substrate between package and IC chips to interconnect various components on the same substrate. However, fine pitch wiring and low resistivity of silicon substrate cause severe noise coupling between interconnects. Therefore, modeling and analysis of noise coupling between TSV silicon interposer interconnects are needed. In particular, RF sensitivity degradation caused by digital noise coupling should be considered when designing mixed-signal silicon interposer. In this paper, modeling of coupled interconnects in TSV silicon interposer is proposed and verified with the fabricated test pattern. A good agreement is found between proposed models and measurement results. Proposed shielding structures for noise coupling suppression are also modeled and verified with the measurement results. In addition, to analyze the noise coupling effect on the Bit-Error-Rate (BER) in the mixed-signal silicon interposer, RF system model in the presence of noise coupling is presented, and a set of design parameters of coupled interconnects to satisfy a target BER in mixed-signal silicon interposer are also presented.